A-Engine / A-Engine-P

A-Engine / A-Engine-P

A-Engine Tech Specs:

  • Measures 3.6×2.3×0.3 inches
  • 16-bit CPU (188), x86 compatible
  • 20/40 MHz system clock
  • Power consumption: 190/130 mA at 5V
  • Power saving mode: 30/25 mA at 5V
  • Up to 512 KB Flash/EPROM
  • Up to 512 KB battery-backed SRAM
  • 2 high-speed PWM outputs, PWD
  • 24 I/O lines from PPI
  • 32 I/O lines from CPU
  • 512 bytes serial EEPROM
  • 8 external interrupt inputs
  • 3 16-bit timers/counters
  • Up to 3 serial ports
  • 11 12-bit ADC (10 kHz sample rate)
  • 2 12-bit DAC
  • Real time clock, battery, watchdog
  • Interface for LCD, keypad

A-Engine-P Tech Specs (adds):

  • Measures 3.6×3.8×0.3 inches
  • RS-232/485 drivers, 5V regulator

General Info

The A-Engine is a C/C++ programmable microprocessor core module (5V only) with a 16-bit 40 MHz CPU.

It supports up to 512 KB ROM/Flash, 512 KB battery-backed SRAM, and a 512-byte EEPROM. A real-time clock (RTC72423) provides information on the year, month, date, hour, minute, second, and 1/64 second. Two DMA-driven serial ports support communication up to 115,200 baud.

The A-Engine can be integrated into an OEM product as a processor core component. It also can be used to build a smart sensor, or a node in a distributed microprocessor system. By building your product around the A-Engine, you reduce the time from design to market introduction, cut development costs, minimize technical risks, and deliver a more reliable product.

There are three 16-bit programmable timers/counters and a watchdog timer. Two timers can be used to count or time external events up to 10 MHz. They can also be used to generate non-repetitive or variable-duty-cycle waveforms as PWM outputs.

The Pulse Width Demodulation (PWD), a distinctive feature, can be used to measure the width of a signal in both its high and low phases. This has potential in a variety of applications, such as bar-code reading.

A-Engine (40 MHz)

Includes 188 processor 40 MHz with 128 KB SRAM, 32 I/Os, 2 UARTs, 3 timers, 82C55 with 24 I/O lines, watchdog timer, 512 byte EE. Does not include add-on options, OEM option discounts available.


  1. SRAM: 512KB
  2. Debug ROM (AC_0_115)
  3. Real-time clock and battery
  4. UART (SCC2691)
  5. 11 ch. 12-bit ADC
  6. 2 ch. 12-bit DAC (LT1446)
  7. VE232 interface board
  8. Sockets for expansion: two 20×2; one 25×2

A-Engine (40 MHz)


  1. UART (SCC2691) w/ drivers: a) RS-232 (default)/b) RS-485


The A-Engine has 32 user-programmable CPU I/O pins, plus 24 bi-directional, user-definable I/O pins from a PPI (82C55) chip. Schmitt-trigger inverters are provided to increase noise immunity for external interrupt inputs. A supervisor chip (691) provides power failure detection and a watchdog timer.

The 12-bit ADC has sample-and-hold, a high-impedance reference input, 11 single-ended 0-5V (or 0 to REF) inputs, and a 10 kHz sample rate. Two 12-bit DAC provide 0 V to 4.095 V analog voltage outputs capable of sinking or sourcing 5 mA. The 82C55 PPI can be used to interface to a 20×4 LCD and keypad or other controllers.

The A-Engine expects a regulated 5V voltage supply, and does not provide RS232 or RS485 drivers for the serial ports. The VE232 can be used to provide this during development/debugging. If you are using this controller stand-alone, you might want to consider the A-Engine-P.

The A-Engine-P is based on the A-Engine design, and offers an on-board 5-volt regulator and two RS-232 drivers, in addition to standard AE features. The third optional UART SCC2691 can be either RS-232 (default) or RS-485, to be specified when ordering. The A-Engine-P does not require the VE232.

The A-Engine shares a similar pin-out and physical dimensions with the 586-Engine, i386-Engine and V25-Engine-LM. Be sure to also check out the A-Engine-86, which is a 16-bit external bus version of the A-Engine. It has almost double the performance capabilities of the original A-Engine.

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