Today, System-on-Chip (SoC) design is becoming more complex as chip designers pack more and more features on to a single device to meet market demands including features, performance and power-consumption requirements.
As process technology improvements reach their limits (the end of Moore’s law), designers are continuing the move to multi-core designs and are integrating different processor architectures (i.e. heterogeneous cores) such as Arm, RISC-V, ARC (Synopsys) and MIPS onto a single SoC.
Ashling’s RiscFree IDE and Debugger provides a full multi-core heterogeneous solution today all from within a single software environment using a single debug probe. Support is currently available for simultaneous, multi-core debug of Arm, MIPS, RISC-V and Synopsys ARC cores.
RiscFree allows full specification of your SoC core configuration and JTAG/cJTAG/Arm Coresight SWD core debug interfaces are supported. RiscFree™ shows dedicated views for each SoC core and these can be easily switched between (or “pinned” for permanent display).