TERN 586-Engine (5E) 100MHZ/133MHZ 32 bit AMD SC520 (586) C/C++ Programmable Controller, with Floating point Unit


586E.jpg (53610 bytes)

586-Engine
high performance 32-bit 586 CPU
with Floating Point Unit (FPU),
ADC, DAC, UARTs, onboard Flash with in System Programming.

586-Engine Specs/Features:
 
  • Includes 133 MHz SC520 with 32 I/Os  1 synch. & 2 asynch.
  • UARTs
  • 3 timers
  • RTC
  • Watchdog timer
  • 256 KW (16-bit) Flash
  • 64 KW (16-bit) SRAM
  • Battery + RTC.
  • Does not include add-on options.
  • OEM option discounts available.

Ordering Information (Qty 1/100/1K)

5E (100 MHz)      $249/$199/$149
Includes 100 MHz SC520 with 32 I/Os, 1 synch. & 2 asynch. UARTs, 3 timers, RTC, watchdog timer, 256 KW (16-bit) Flash, 64 KW (16-bit) SRAM, battery + RTC.   Does not include add-on options. OEM option discounts available.

EV-P/DV-P Kit $349/$799
Software & 586-Engine
 


 
Quantity Price
1 $199
50 $175
100 $149
1,000+ $99

 
   
Add-on Options:  
1.- SRAM: 256KW (512KB) $40
2.- UART (SCC2691) $20
3.- 11 ch. 12-bit ADC $20
4.- 8 ch. 12-bit ADC (AD7852) $20
5.- Dual 12-bit DAC (LT1446), up to 2 $20 ea
6.- Quad 12-bit DAC (DA7625) $40
7.- VE232 interface board $69

 

The 586-Engine (5E) is a C/C++ programmable controller based on a 32-bit 100/133 MHz AMD Elan SC520 that integrates an Am586 CPU and an ANSI/IEEE 754 compliant 64-bit hardware FPU. A unique 16-bit parallel ADC (AD7655, 0-5V) supports ultra highspeed (1 MHz conversion rate) analog signal acquisition. The AD7655 contains 2 low noise, high bandwidth track-and-hold amplifiers that allow simultaneous sampling on 2 channels.

The SC520 integrates an Am586 CPU and a high performance ANSI/IEEE 754 compliant hardware floating point unit (FPU). The SC520 has a total of seven timers including PIT timers and GP timers, plus a software timer. A real-time clock (RTC) provides a time-of-day calendar and 114 bytes of battery backed RAM. 13 user programmable multifunctional I/O lines are available. One synchronous serial interface (SSI) supports full-duplex, high speed bi-directional communication.
 

The SC520 supports 32 programmable multifunctional I/O lines (PIO) that can be used as general discrete I/O. Up to industrial standard 16550-compatible UARTs (w/ RS232 drivers) support baud rates up to 1.152 M baud. Two UARTs can be configured with RS485 drivers. One synchronous serial interface (SSI) supports full-duplex, high speed bi-directional communication.

By default, 256KW low power 55 ns SRAM is installed to allow longer battery backup lifetime; this requires slower 2 wait state access to memory. Optionally, if battery backup is not required, a higher speed 20 ns SRAM can be installed to allow higher performance zero wait state operation.

In additional to the on-board surface mount Flash, a 32-pin DIP IC socket allows using traditional user application plug-in ROM/Flash. A 50-pin CompactFlash interface supports low cost, removable, up to 2 GB mass storage CompactFlash cards with Windows compatible FAT file system support. The 5D can be powered by a single unregulated DC power from 8V to 30V range with the on-board high-efficiency 5V switching regulator.

The 586-Engine shares a similar pin-out and physical dimensions with the i386-Engine, A-Engine and V25-Engine-LM.  As compared to these other engine-based controllers, the 5E offers substantially more computing power at greater per-unit costs and power requirements.

The 388 pin BGA package of the SC520 CPU makes repair support for the 586-Engine not available.

 586P100.jpg (60177 bytes)
586-Engine with P100 Expansion Board

 

 

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